Title  

The minimum number of transistors required to implement a two input AND gate isThe minimum number of transistors required to implement a two input AND gate is
The answer is:
C. 6


Using DeMorgan’s Theorem we can convert any ANDOR structure intoUsing DeMorgan’s Theorem we can convert any ANDOR structure into
The answer is:
A. NANDNAND


For a memory with a 16bit address space, the addressability isFor a memory with a 16bit address space, the addressability is
The answer is:
D. Cannot be determined


Because we wish to allow each ASCII code to occupy one location in memory, most memories are_____ addressableBecause we wish to allow each ASCII code to occupy one location in memory, most memories are_____ addressable.
The answer is:
A. BYTE


Circuit A is a 1bit adder; circuit B is a 1 bit multiplier. (Hint: Construct the truth table for the adder and the multiplier)Circuit A is a 1bit adder; circuit B is a 1 bit multiplier. (Hint: Construct the truth table for the adder and the multiplier)
The answer is:
A. Circuit A has more gates than circuit B


When the write enable input is not asserted, the gated D latch ______ its outputWhen the write enable input is not asserted, the gated D latch ______ its output
The answer is:
A. can not change


A structure that stores a number of bits taken “together as a unit” is aA structure that stores a number of bits taken “together as a unit” is a
The answer is:
D. register


We say that a set of gates is logically complete if we can build any circuit without using any otherkind of gates. Which of the following sets are logically completeWe say that a set of gates is logically complete if we can build any circuit without using any otherkind of gates. Which of the following sets are logically complete
The answer is:
C. set of {AND,OR,NOT}


Of the following circuits, the one which involves storage isOf the following circuits, the one which involves storage is
The answer is:
A. RS Latch


If m is a power of 2, the number of select lines required for an minput mux is:If m is a power of 2, the number of select lines required for an minput mux is:
The answer is:
C. log2 (m)


For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2]For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2].
The answer is:
C. the same as


Which of the following conditions is not allowed in an RS latch?Which of the following conditions is not allowed in an RS latch?
The answer is:
A. R is asserted, S is asserted


Which of the following pair of gates can form a latch?Which of the following pair of gates can form a latch?
The answer is:
C. a pair of cross coupled NAND


‘Burst refresh’ in DRAM is also called‘Burst refresh’ in DRAM is also called
The answer is:
A. Concentrated refresh


The number of interrupt lines in 8085 is 

A real number consists ofA real number consists of
The answer is:
C. integer part, fraction part along with positive or negative sign


Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran. Reason (R): Fortran 77 has better array facilities than earlier versions of FortranAssertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran. Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran.
The answer is:
B. Both A and R are correct but R is not correct explanation of A


Which of the following is not treated as hexadecimal constant by assembler in 8085?Which of the following is not treated as hexadecimal constant by assembler in 8085?
The answer is:
C. 234


IC 7485 cannot be cascadeD 

An I/O processor controls the flow of information betweenAn I/O processor controls the flow of information between
The answer is:
B. main memory and I/O devices

MCQs
Views
Best Answers
Points